The present invention relates in general to a three phase inverter circuit wherein a plurality of switching devices are turned on and off to convert a dc voltage to a three phase ac voltage and, more particularly, to a method for operating such an inverter circuit to provide improved transition from a space vector pulse width modulation (SVPWM) operating mode to a six step operating mode.
FIG. 1 illustrates an inverter circuit 100 including six switching devices SA+, SA-, SB+, SB-, SC+ and SC- connected into a bridge circuit between circuit buses 102 and 104 which are maintained at .+-.V.sub.dc /2, respectively, relative to a virtual neutral point in a manner common in the art. The switching devices are operated by a pulse width modulation (PWM) switching driver circuit 106 in response to a command vector V.sub.s * to construct three phase ac power for a three phase load, such as the three phase motor 108, from a source of dc voltage V.sub.dc.
Since either the upper or the lower switching device of each of the three legs of the inverter circuit 100 is turned on, the switching states of the inverter circuit 100 can be represented by three binary numbers (SA, SB, SC). For this representation, a "1" indicates that the upper or + switching device is on and a "0" indicates that the lower or - switching device is on. Thus, (0, 0, 0) indicates that SA-, SB- and SC- are on and SA+, SB+ and SC+ are off; (1, 0, 0) indicates that SA+, SB- and SC- are on and SA-, SB+ and SC+ are off; and so on.
The eight resulting switching or voltage vectors V0 through V7 are shown in FIG. 2 with (0, 0, 0) or V0 and (1, 1, 1) or V7 being zero vectors. The hexagon spanned by the six non-zero voltage vectors V1 through V6 can be divided into six regions, 1 through 6, with each region being spanned by two of the non-zero voltage vectors. The magnitude or length of each non-zero voltage vector is equal to 2V.sub.dc /3 where V.sub.dc is again the magnitude of the source of dc voltage.
Vectors can be represented by their projections onto X and Y axes superimposed onto the hexagon spanned by the vectors V1 through V6. For example, the voltage command vector V.sub.s * can be projected to define V.sub.x * and V.sub.y * as shown in FIG. 3. The projections of each non-zero vector onto the X and Y axes can be determined from the equations : EQU V.sub.i,x =2V.sub.dc /3[cos ((i-1)60.degree.] (1) EQU V.sub.i,y =2V.sub.dc /3[sin ((i-1)60.degree.] (2)
where i is the index of the vectors, i.e, i=1 represents voltage vector V1, i=2 represents voltage vector V2, and so forth; i can also be interpreted as the index for the regions 1 through 6.
A number of known pulse width modulation (PWM) control arrangements are used to control the switching devices SA+, SA-, SB+, SB-, SC+ and SC- to generate a three phase balanced set of ac voltages from the fixed dc voltage V.sub.dc. One commonly used switching arrangement for generating the gating patterns for three phase operation is known as space vector pulse width modulation (SVPWM). For this arrangement, a balanced three phase voltage command is represented by a voltage command vector rotating in the X-Y plane. Thus, for each pulse width modulation control period (TPWM), a three phase voltage command is represented by a voltage command vector in the X-Y plane spanned by the six non-zero voltage vectors V1 through V6 available from the inverter circuit 100. Each voltage command vector is then approximated or constructed by combining properly proportioned vectors which are aligned with the two adjacent non-zero vectors and an appropriate one of the zero vectors, V0 or V7.
For example, as shown in FIG. 3, the voltage command vector V.sub.s * is approximated by V.sub.1 *, V.sub.2 * and one of the zero vectors, V0 or V7. Zero vectors preferably are chosen so that only one of the switching devices SA+, SA-, SB+, SB-, SC+ and SC- needs to change its on/off state for each transition from one non-zero vector to the zero vector to the next non-zero vector. The size or time span for each of the voltage vectors is selected to balance the volt-seconds commanded by the command vector and the actual volt-seconds applied by the inverter circuit 100. To this end, t1 represents the time duration of Vi, t2 represents the time duration of Vi+1 and t0 represents the time duration of the zero vector, V0 or V7. In order to maintain the volt-second balance, the following vector equation must be satisfied: EQU V.sub.s *.multidot.TPWM=Vi.multidot.t1+V(i+1).multidot.t2+0.multidot.t0(3)
where t1+t2+t0=TPWM. In terms of X-Y components: EQU V.sub.x *.multidot.TPWM=V.sub.i,x .multidot.t1+V.sub.i+1,x .multidot.t2+0.multidot.t0 (4) EQU V.sub.Y *.multidot.TPWM=V.sub.i,y .multidot.t1+V.sub.i+1,y .multidot.t2+0.multidot.t0 (5)
Using equations (1), (2), (4) and (5), the space vector PWM times t1, t2 and t0 can be determined by solving the following equations: EQU t1=.sqroot.3.multidot.TPWM/V.sub.dc [sin(i.multidot.60.degree.)V.sub.x *-cos(i.multidot.60.degree.)V.sub.y *] (6) EQU t2=.sqroot.3.multidot.TPWM/V.sub.dc [-sin((i-1)60.degree.)V.sub.x *+cos((i-1)60.degree.)V.sub.y *] (7) EQU t0=TPWM-t1-t2 (8)
where i is the region index, 1 through 6, for example, i=1 is for voltage command vectors which lie between V1 and V2, i=2 is for voltage command vectors which lie between V2 and V3, and so on as illustrated in FIG. 3. While space vector pulse width modulation (SVPWM) as described is well known to those skilled in the art, those desiring a more in depth understanding and analysis are referred to H. W. van der Broeck et al., "Analysis and Realization of a Pulse Width Modulator Based on Voltage Space Vectors", IEEE/IAS 1986 Annual Meeting, pp. 244-251.
It can be shown that SVPWM can achieve a linear range of control as long as the magnitude of the voltage command vector V.sub.s * is less than or equal to (1/.sqroot.3).multidot.V.sub.dc. Graphically, this linear control area corresponds to the inside of the circle imposed within the hexagon of FIG. 3. Unfortunately, if the magnitude of the voltage command vector V.sub.s * is greater than V.sub.dc .sqroot./3, t0 can be negative indicating that zero vectors can no longer be applied. In this case, t1+t2 is greater than TPWM and truncation of t1 and/or t2 is necessary. Accordingly, SVPWM starts to drop zero vectors with more and more zero vectors being dropped as the magnitude of the voltage command vector V.sub.s * is increased. FIG. 4 illustrates a phase voltage waveform generated in a linear PWM mode of operation. FIG. 5 illustrates a phase voltage waveform generated in a pulse dropping mode of operation just described. And, FIG. 6 illustrates a standard six step mode of operation which results in the highest possible fundamental component and hence represents the best utilization of available dc voltage.
It is desirable to switch to the six step mode of operation when V.sub.s * becomes greater than V.sub.dc /.sqroot.3. Unfortunately, a jump in control directly to the six step mode of operation creates a large disruptive transient in the three phase voltage being generated. Another common arrangement for handling excessive magnitude of the voltage command vector V.sub.s * is to truncate both t1 and t2 proportionally so that the phase angle of the voltage command vector is maintained. For this arrangement, EQU t1=[t1/(t1+t2)].multidot.TPWM, and (9) EQU t2=[t2/(t1+t2)].multidot.TPWM. (10)
Unfortunately, this arrangement can not achieve full six step operation.
In U.S. Pat. No. 5,182,701, another arrangement for handling excessive magnitude of the voltage command vector V.sub.s * is disclosed wherein half of the t0 value is subtracted from both t1 and t2. While this arrangement will ultimately result in full six step operation, the magnitude of the voltage command vector V.sub.s * must be very large to result in six step operation and the transition is long and drawn out. Accordingly, there is a need for an improved arrangement for performing transition from SVPWM operation of an inverter circuit to six step operation.